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VPR
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PCIe Channelized DMA Compatible BiDirectional Serial Data Interface Card
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| Publication
date on this website:
30/10/2009 |
| Category:
Boards |
| Company:
Dynamic Engineering |
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| Summary: |
<p style="text-align: left">PCIeBiSerialDB37 is PCI Express native with 1-4 lanes used. The DB37 connector is mounted to allow cabling directly to the rear port of the PC <em><span style="font-size: smaller">(DB37 connectors allow for a variety of wiring - twisted pair, twin-ax, ribbon etc.)</span></em> PCIeBiSerialDb37 can be configured with RS-485/RS-422, LVDS or both types of IO. Each IO is individually programmable for direction and termination. All IO are matched length and impedance controlled from the FPGA to the connector cable mounting plane to allow for any client requirement: Full Duplex, Half-Duplex, Parallel, Serial, multi-channel etc. The hardware is optimized with channelized DMA to allow for efficient data movement to and from the host memory. Additional HW features include a 4 channel PLL, internal and external memory, local power supplies etc. Call us with your requirements for the <strong>PCIeBiSerialDb37</strong>.</p>
<p style="text-align: left"><a href="http://www.dyneng.com/pciebiserialdb37.html">http://www.dyneng.com/pciebiserialdb37.html</a> </p> |
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| Full
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<p>PCIeBiSerialDb37 Features</p>
<p>Size:  Standard 1/2 length PCIe card<br />
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 IO Speeds:  Up to 40 MHz RS485, and up to 200 MHz LVDS signaling supported. Clock generator and PLL. PLL has 4 programmable outputs connected to the FPGA. 50 MHz reference for PLL with alternate frequencies available.<br />
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 PCI Speed:  Standard 33 MHz. operation over the Industrial temperature range. 50 MHz for commercial temperature designs. Channelized DMA.<br />
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 PCIe Speed:  1-4 lane operation.<br />
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 PCI Access Width:  Standard 32 bit operation supported.<br />
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 Software Interface:  Registers are read-writeable. Transmit and Receive functions separated. Base functions separated. Flat or heirarchical applications supported. Windows® and Linux drivers support heirarchical access. With each interface independent each interface is less complex to control. <br />
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Interrupts:  Transmit and Receive state-machine, FIFO Programmable almost empty [transmit] and programmable almost full [receive] . Programmable interrupts on error conditions [overflow, underflow, parity, etc.]. DMA is supported with interrupts. All interrupts are maskable and status can be polled for non-interrupt driven operation. <br />
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 Signaling:   18 RS-485 / RS-422 / LVDS compatible IO are provided. Any combination of transmit or receive channels can be created. LVDS and RS-485 can be mixed. RS-485 bandwidth is lower when mixed [16 MHz]. Programmable termination. Pull-up and Pull-down option on IO to allow controlled level when tri-stated. Option for high or low state. 3.3V RS-485 can be used for lower power consumption.<br />
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 IO:  The IO is available via the bezel connector - DB37. The differential IO is properly routed with impedance control, pitch, and space plus matched lengths across all of the pairs.   <br />
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Interface: Custom programmed interfaces available. Send  a timing diagram, for your custom  program. Most interfaces can be adapted from our large library of designs within 1-2 weeks including the updated VHDL, Windows/Linux Driver, reference manuals etc.   <br />
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Power:  +12 and 3.3V from PCIe connector. Local 5V, 2.5V and 1.2V converted with on-board power supplies. No power cables are required for this design.<br />
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Memory:  Separate FIFOs / Dual Port RAM are provided for all channels. Internal FPGA Block RAM memory modules for fast access. Optional discrete FIFO´s [128K x 32] available.<br />
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FPGA: Xilinx Spartan III 2000 and 4000 models are installed based on client requirements. <br />
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 Speed: Optimized for serial interfacing requirements. FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. The FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the BiSerial has independent channel functions. Channels can operate at maximum rate in parallel. With the Spartan III Channelized DMA can be implemented and still have plenty of gates left for your application.<br />
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 Price:  The BiSerial is easily programmed to implement new functions. Many previously implemented custom designs are available too. Without the costs of schematic level design, layout, debugging etc. a modified BiSerial will represent a large cost savings in your budget.<br />
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Ease of Use:  PCIeBiSerialDb37 is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and engineering kits help with integration into your system. Custom Windows® or Linux driver also available. <br />
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Availability:  Dynamic Engineering works to keep the PCIeBiSerialDb37 in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with the another version then send updated FLASH Files later to help get your project going - right away. Please note that there may be some delay for designs using client defined mixed IO etc.<br />
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Size:  PCIeBiSerialDb37 is a standard1/2 length PCIe card and meets the PCIe mechanical specifications. The PCIeBiSerialDb37 can be used in all PCIe slots with 4 or more lanes. We can cut-down the PCIe connector for 1 lane implementations. The edge of the PCIeBiSerialDb37 is clear to allow for horizontal mount industrial chassis applications.<br />
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PCIe Compatibility: PCIe compliant per the PCI-SIG specification.  <br />
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PCI Compatibility: PCI compliant. PCIeBiSerialDb37 uses a Tundra PCIe 4 lane bridge to PCI for the PCIe connection and PCI interface contained within the FPGA.<br />
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| Contact: |
<p style="text-align: left">Dynamic Engineering<br />
(831) 457-8891<br />
<a href="http://www.dyneng.com">www.dyneng.com</a><br />
<a href="mailto:sales@dyneng.com">sales@dyneng.com</a></p>
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